In analog memory devices, a set of thresholds is often used for reading data stored in the memory cells. The process of adjusting the thresholds may be affected by the prevalence of one-bits versus zero-bits in the stored data.
Sulaiman Al-Bassam et al. present balanced codes in “On balanced codes,” IEEE Transactions on Information Theory, March, 1990, volume 36 (issue 2), pages 406-408, which is incorporated herein by reference. The paper discusses balanced code wherein each codeword contains an equal number of 1's and 0's. Parallel decoding balanced codes with 2r (or 2r−1) information bits are presented, where r is the number of check bits.
In “Balanced Modulation for Nonvolatile Memories,” in Computing Research Repository (CoRR, 2012), which is incorporated herein by reference, Hongchao Zhou et al. present a practical writing/reading scheme in nonvolatile memories, called balanced modulation, for minimizing the asymmetric component of errors. The scheme encodes data using a balanced error-correcting code. When reading information from a block, the scheme adjusts the reading threshold such that the resulting word is also balanced or approximately balanced.
Zhou et al. present schemes with dynamic thresholds in “Error-Correcting Schemes with Dynamic Thresholds in Nonvolatile Memories,” Proceedings of the 2011 IEEE International Symposium on Information Theory (ISIT 2011), St. Petersburg, Russia, July 31-Aug. 5, 2011, pages 2143-2147, which is incorporated herein by reference. The authors construct error-correcting schemes with dynamic reading thresholds, so that the asymmetric component of errors are minimized. Additionally, the authors discuss how to select dynamic reading thresholds without knowing cell level distributions, and present several error-correcting schemes.
U.S. Pat. No. 8,059,439, whose disclosure is incorporated herein by reference, discloses an encoding scheme that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. The encoded data words can be balanced data words that have equal number of logic high and logic low values.
U.S. Pat. No. 8,000,161, whose disclosure is incorporated herein by reference, describes a method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.